74HC00 Datasheet by ON Semiconductor

0N Semimnductor® H H H H H H H 14$ In Compliance wnn me JEDEC Standard No. 7A Requirements ‘ £32522; 0 AWLYW 2000 v; Machine Model > 200 v H H H H H H H H H H H H H H Q TSSOP-14 1 4 DT SUFFIX 3)— \ ‘ CASE 94m. 0 ”(W H H H H H H : HCOO : Dewce Code v : n; A Assembly Lacation WL or L Waler Lo‘ 30— Y : Year WW or W Work Week G 0! - : Pb-Free Package FUNCTION TABLE 5 (Top View) Inputs Output V VH—H—ll—II—ITH—V IIr—r—> Ir—Ir—m r-III L1 L1 |_| |_| |_| LI Ll ORDERING INFORMATION D See detailed nrdeung and shwppmg mmmanun m we dwmensmns secuon on page 2 cu (ms data sham 1 Publicatlan Oldel 74

© Semiconductor Components Industries, LLC, 2007

March, 2007 - Rev. 1

1Publication Order Number:

74HC00/D

74HC00

Quad 2-Input NAND Gate

High-Performance Silicon-Gate CMOS

The 74HC00 is identical in pinout to the LS00. The device inputs are

compatible with Standard CMOS outputs; with pullup resistors, they

are compatible with LSTTL outputs.

Features

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS and TTL

•Operating Voltage Range: 2.0 to 6.0 V

•Low Input Current: 1.0 mA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance With the JEDEC Standard No. 7A Requirements

•ESD Performance: HBM > 2000 V; Machine Model > 200 V

•Chip Complexity: 32 FETs or 8 Equivalent Gates

•These are Pb-Free Devices

3Y1

PIN 14 = VCC

PIN 7 = GND

LOGIC DIAGRAM

6Y2

8Y3

11 Y4

Y = AB

Pinout: 14-Lead Packages (Top View)

1314 12 11 10 9 8

21 34567

VCC B4 A4 Y4 B3 A3 Y3

A1 B1 Y1 A2 B2 Y2 GND

MARKING

DIAGRAMS

HC00 = Device Code

A = Assembly Location

WL or L = Wafer Lot

Y = Year

WW or W = Work Week

G or  = Pb-Free Package

FUNCTION TABLE

Inputs Output

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

ORDERING INFORMATION

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TSSOP-14

DT SUFFIX

CASE 948G

SOIC-14

D SUFFIX

CASE 751A

HC00G

AWLYWW

ALYW



(Note: Microdot may be in either location)

74HC00

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MAXIMUM RATINGS

Symbol Parameter Value Unit

VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V

Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V

Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V

Iin DC Input Current, per Pin ±20 mA

Iout DC Output Current, per Pin ±25 mA

ICC DC Supply Current, VCC and GND Pins ±50 mA

PDPower Dissipation in Still Air, SOIC Package†

TSSOP Package†

500

450

Tstg Storage Temperature – 65 to + 150 C

TLLead Temperature, 1 mm from Case for 10 s

SOIC or TSSOP Package 260

C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

†Derating — SOIC Package: – 7 mW/C from 65 to 125C

TSSOP Package: - 6.1 mW/C from 65 to 125C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High- Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

Vin, Vout DC Input Voltage, Output Voltage

(Referenced to GND)

0 VCC V

TAOperating Temperature, All Package Types – 55 + 125 C

tr, tfInput Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

1000

500

400

ORDERING INFORMATION

Device Package Shipping†

74HC00DR2G SOIC-14

(Pb-Free) 2500/Tape & Reel

74HC00DTR2G TSSOP-14*

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb-Free.

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high-impedance

circuit. For proper operation, Vin and

Vout should be constrained to the

range GND v (Vin or Vout) v VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

74HC00

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DC CHARACTERISTICS (Voltages Referenced to GND)

VCC

(V)

Guaranteed Limit

Symbol Parameter Condition -55 to 25°C≤85°C≤125°C Unit

VIH Minimum High-Level

Input Voltage

Vout = 0.1V or VCC -0.1V

|Iout| ≤ 20mA

2.0

3.0

4.5

6.0

1.50

2.10

3.15

4.20

1.50

2.10

3.15

4.20

1.50

2.10

3.15

4.20

VIL Maximum Low-Level

Input Voltage

Vout = 0.1V or VCC - 0.1V

|Iout| ≤ 20mA

2.0

3.0

4.5

6.0

0.50

0.90

1.35

1.80

0.50

0.90

1.35

1.80

0.50

0.90

1.35

1.80

VOH Minimum High-Level

Output Voltage

Vin = VIH or VIL

|Iout| ≤ 20mA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

Vin =VIH or VIL |Iout| ≤ 2.4mA

|Iout| ≤ 4.0mA

|Iout| ≤ 5.2mA

3.0

4.5

6.0

2.48

3.98

5.48

2.34

3.84

5.34

2.20

3.70

5.20

VOL Maximum Low-Level

Output Voltage

Vin = VIH or VIL

|Iout| ≤ 20mA

2.0

4.5

6.0

0.1

Vin = VIH or VIL |Iout| ≤ 2.4mA

|Iout| ≤ 4.0mA

|Iout| ≤ 5.2mA

3.0

4.5

6.0

0.26

0.33

0.40

Iin Maximum Input Leakage

Current

Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA

ICC Maximum Quiescent Supply

Current (per Package)

Vin = VCC or GND

Iout = 0mA

6.0 2.0 20 40 mA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High- Speed CMOS Data Book

(DL129/D).

AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

VCC

(V)

Guaranteed Limit

Symbol Parameter -55 to 25°C≤85°C≤125°C Unit

tPLH,

tPHL

Maximum Propagation Delay, Input A or B to Output Y

(Figures 1 and 2)

2.0

3.0

4.5

6.0

110

tTLH,

tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 2)

2.0

3.0

4.5

6.0

110

Cin Maximum Input Capacitance 10 10 10 pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON

Semiconductor High- Speed CMOS Data Book (DL129/D).

CPD Power Dissipation Capacitance (Per Buffer)*

Typical @ 25°C, VCC = 5.0 V, VEE = 0 V

* Used to determine the no- load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

ON Semiconductor High- Speed CMOS Data Book (DL129/D).

74HC00

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Figure 1. Switching Waveforms

GND

VCC

OUTPUT Y

INPUT

A OR B

CL*

*Includes all probe and jig capacitance

TEST

POINT

90%

50%

10%

tTLH

DEVICE

UNDER

TEST

OUTPUT

Figure 2. Test Circuit

Figure 3. Expanded Logic Diagram

(1/4 of the Device)

tTHL

90%

50%

10%

tPLH tPHL

tftr

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74HC00

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PACKAGE DIMENSIONS

SOIC-14

CASE 751A-03

ISSUE H

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.127

(0.005) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

-A-

-B-

P7 PL

14 8

0.25 (0.010) B M

0.25 (0.010) A S

-T-

RX 45

SEATING

PLANE D14 PL K

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A8.55 8.75 0.337 0.344

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.228 0.244

R0.25 0.50 0.010 0.019

 

7.04

14X

0.58

14X

1.52

1.27

DIMENSIONS: MILLIMETERS

PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb-Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

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74HC00

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PACKAGE DIMENSIONS

TSSOP-14

CASE 948G-01

ISSUE B

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A4.90 5.10 0.193 0.200

B4.30 4.50 0.169 0.177

C--- 1.20 --- 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.50 0.60 0.020 0.024

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL

NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE -W-.



U0.15 (0.006) T

2X L/2

0.10 (0.004) V S

L-U-

SEATING

PLANE

0.10 (0.004)

-T-

SECTION N-N

DETAIL E

JJ1

DETAIL E

-W-

0.25 (0.010)

PIN 1

IDENT.

U0.15 (0.006) T

-V-

14X REFK

7.06

14X

0.36 14X

1.26

0.65

DIMENSIONS: MILLIMETERS

PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb-Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

Semxcanduclm and J

74HC00

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights

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Phone: 81-3-5773-3850

74HC00/D

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